zener-ngspice-bench

Builds and runs single-purpose ngspice testbenches for Zener hardware packages through the pcb sim command. Covers binding SPICE models to leaf components, writing stimulus, analysis and measurement directives as raw ngspice, reading trustworthy numbers out of the verbose transcript, and exporting a netlist for runs that exceed the built-in five-second cap. Use when asked to simulate, verify or characterize one specific circuit behavior such as power-up sequencing, enable timing, a protection trip point, or current limiting, or to attach a vendor SPICE model to a part. Not for Verilog-A or encrypted models, layout, routing, or signal-integrity work.

Version

v1.0.0

Size

12 KB

Updated

2026-10-07

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